1. Field of the Invention
The present invention relates to sensing circuits for sensing the state of a memory cell, e.g., in an EEPROM, and more specifically to a method and apparatus for on-chip adjustment of the reference current supplied to the sense amplifier in the sensing circuit.
2. Description of Related Art
As is known in the art, individual cells in an EEPROM are sensed to determine the state of the memory cell using a sensing amplifier. Typically EEPROMs are constructed using a floating gate MOS transistor, with the floating gate charged to a xe2x80x9cprogrammed levelxe2x80x9d to indicate the presence of a logic xe2x80x9czeroxe2x80x9d in the memory cell, or xe2x80x9cerasedxe2x80x9d of charge leaving a lower level of charge on the floating gate to indicate the presence of a logic xe2x80x9czeroxe2x80x9d in the memory cell. The state of the charge on the floating gate modifies the threshold voltagd Vt (gate to source) applied to the control gate of the floating gate MOS transistor, at which the floating gate MOS transistor will turn on. The result is a reading of a logic xe2x80x9czeroxe2x80x9d if the floating gate is charged, because the higher resulting threshold voltage causes the cell not to turn on and conduct when the control gate (connected to an associated word line in the memory array) is pulled up. On the other hand, the lower charge on the floating gate (and resulting lower threshold voltage) enables the word line to turn on the floating gate MOS transistor of the cell when the word line is pulled up.
Those skilled in the art will appreciate the need to precisely adjust the reference current supplied to the sensing circuit of an EEPROM in order to provide a voltage on the word line to the particular cell that is effective to turn on the cell transistor when the floating gate is at the lower charged state and not to turn on the floating gate transistor when the floating gate is at the more highly charged state. In addition to the charge on the floating gate, (which itself can vary with such factors as manufacturing process variations, supply voltage Vcc variation and environmental changes, e.g., temperature), there are other influences upon the threshold voltage of each of the floating gate EEPROM memory cell transistors, including manufacturing process variations.
In the case where the reference current supplied is inadequate to supply the appropriate voltage to turn the floating gate MOS transistor of the memory cell on at the appropriate time and/or not turn it on at the appropriate time, based upon the level of charge stored in the floating gate as representing the programmed or erased state, then the cell is useless. Depending upon the design of the memory, e.g., an EEPROM, the faulty cell can cause the inability to use a section of the memory array or the entire memory array, with the obvious impact on yields of the devices in the manufacturing process.
There exists a need, therefore for the ability to correct on a chip-by-chip basis the impact of variable reference currents resulting from, e.g., fabrication processing variations, in order to prevent the deleterious effects of the reference current variations.
The present invention, therefore, provides a method and apparatus for adjusting on a chip-by-chip basis the reference current that is supplied to the sensing circuitry. The disclosed method and apparatus provide a memory circuit having a sense amplifier connected to read the data content output of a memory cell, and wherein the sense amplifier includes a current source transistor having a gate and having a drain connected to a voltage supply and having a source connected to the respective bit line, with a selectable source current in order to account for variations from a desired source current due to variations in the designed source current transistor performance parameters. The apparatus and method comprise providing a variable reference voltage with a variable reference voltage generating circuit having an output voltage coupled to the gate of the sense amplifier source transistor, wherein the variable reference voltage generating circuit comprising: a current source transistor having an input connected to the voltage supply and an output connected to the output of the variable reference voltage generating circuit and to a current divider network; the current divider network comprising a plurality of variable current flow arms each having a selection transistor for selecting the respective current flow arm to pass current or not pass current; and, wherein each of the respective current flow arm selection transistors is controlled by a respective bit in a plurality of bits stored in a non-volatile on-chip memory location. The variable reference voltage is buffered to provide a low impedance connection of the voltage to the gates of the respective sense amplifier source current transistors. The variable reference voltage generating circuit source current transistor and the respective sense amplifier current source transistors are selected such that the application of the variable reference voltage produced according to the present method to the gate of the sense amplifier current source transistor will produce essentially the same current through the sense amplifier current source transistor as the total current generated in producing the variable reference voltage.